The LVDS-Analyzer was developed as part of a test system. With the Analyzer, the digital color information of any video line within an image can be recorded and evaluated. In addition, the 2-wire LVDS signal is de-serialized and the contained information is recorded. The test image can be forwarded 1 to 1 on a reference display or own test images can be emitted onto under test LVDS sinks
General info:
- 5V power supply via the USB port
- Controlling and multiplexing via USB 2.0 (also upon request via RS232)
- Use of diagnostic and control functions of the LVDS serialize and de-serializer as follows:
- LVDS cable fault detection (short circuit, interruption) on the LVDS output
- Detection of established connection (Lock-Signal) on the LVDS input
- Distance configuration of the LVDS receiver on input/output (must be supported by this)
- De-serializer and serializer via USB on and off switchable during other especially noise-sensitive test procedures
LVDS input:
- De-serialization of the LVDS data streams with MAX9260 of Maxim Integrated Products Inc.
- De-mapping of the received video data stream in RGB data, HSYNC and VSYNC
- Analogous edition of the I² S-audio data stream via digital/analog converter.
- Serialized LVDS edition of the video and audio input data stream via MAX9259 of Integrated Products Inc.
- Remapping of the output data stream of different target devices (displays) possible.
- Measuring of the picture geometry by means of logging of HSYNC,VSYNC and pixel clock.
- Logging of a video line in full solution with up to 2047 pixels.
- RGB color solution up to 24Bit
- Logging of statue per multiple line scanning possible.
- Reducing the resolution to increase the measuring speed possible
LVDS output:
- Freely definable beam test picture with up to 2047 pixels width and up to 2047 lines height; also horizontal gray and color gradient possible
- RGB color resolution up to 24Bit
- Mapping of the color and synchronous signals to the target device (LVDS-sink)
- Synchronized to the synchronous signals of the input
- Generating its own synchronous signals HSYNC, VSYNC, and DATA ENABLE from the pixel clock?
- Alternatively, pixel clock from the input signal or its own clock generator (18MHz, 27MHz, 29MHz, 36MHz, 54MHz, 58MHz)
